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INTEGRATED CIRCUITS
DATA SHEET
SAA7346 Shock absorbing RAM addresser
Preliminary specification File under Integrated Circuits, IC01 July 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
FEATURES * Absorbs shocks from x, y and z directions * Absorbs rotational shocks * Absorbs multiple shocks per second * Interfaces directly to compact disc decoders SAA7345, SAA7347 and SAA7370 * Multi-speed I2S-bus input with single-speed I2S-bus output * Controls 1 or 4 MBit of external Dynamic Random Access Memory (DRAM) * Easy serial interface for communication with common microcontrollers * Software selectable shock detectors * By-pass/power-down mode * Kill interface for DAC deactivation * Can be used for: - `sampling' part of a disc - to reduce access pauses between jumps - to deliver a programmable delay - to generate a fixed audio rate from Constant Angular Velocity (CAV) discs. QUICK REFERENCE DATA SYMBOL VDD IDD fclk fi(clk) fo(clk) Tamb Tstg PARAMETER supply voltage supply current clock frequency I2S input word clock frequency I2S output word clock frequency operating ambient temperature storage temperature - - 44.1 44.1 -40 -65 MIN. 3.3 12 16.9344 88.2 88.2 - - TYP. 5.0 - - 176.4 176.4 +85 +150 GENERAL DESCRIPTION
SAA7346
The SAA7346 can be used to make a CD player insensitive to shocks. To do this, SAA7346 operates closely with a standard 1 Mbit or 4 Mbit DRAM. Audio data is stored inside the DRAM and during shocks the data of the DRAM can be played. The SAA7346 functions as a customized DRAM controller with serial I/O and on-board shock detectors.
MAX. 5.5 V
UNIT mA MHz kHz kHz C C
ORDERING INFORMATION PACKAGE TYPE NUMBER PINS SAA7346H Note 1. When using reflow soldering it is recommended that the Dry Packing instructions in the "Quality Reference Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011. 44 PIN POSITION QFP(1) MATERIAL plastic CODE SOT307-2
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Preliminary specification
Shock absorbing RAM addresser
BLOCK DIAGRAM
SAA7346
S_NSF
handbook, full pagewidth
D0 to D3
KILLOUT
SCLO
V DD1
3
4
5
2
1
42 to 39
19 13
21 20 22
23 44
I 2S INPUT
DATA MULTIPLEXER
I 2S OUTPUT
SAA7346
RESET TMS 14 8 WRITE POINTER REGISTER 16 15 17 ADDRESS MULTIPLEXER
32, 30, 28, 26, 25, 27, 29, 31, 33, 34
V DD2
CFLG
SCLI
KILL
WCO
SDO
WCI
SDI
A0 to A9
READ POINTER
SICL SIDA SILD
6 MICROCONTROLLER INTERFACE MONITOR CONTROLLER 18
CONFIG FILL
SHOCK DETECTORS 24 43 9 OTD 11 12 SSD RSB 36 37 38 35 RAS CAS WE OE
TIMING
7 CLKIN
10
MGB429
VSS1 VSS2
Fig.1 Simplified SAA7347 block diagram.
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RCD2
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
PINNING SYMBOL CFLG KILL SCLI WCI SDI CONFIG CLKIN TMS OTD RCD2 SSD RSB S_NSF RESET SIDA SICL SILD FILL KILLOUT SDO SCLO WCO VDD1 VSS1 A4 A3 A5 A2 A6 A1 A7 A0 A8 A9 OE RAS CAS WE PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 kill input multi-speed I2S bit clock input multi-speed I2S word clock input multi-speed I2S data input external DRAM select input; HIGH 4 Mbit, LOW 1 Mbit 16.9344 MHz system clock input test mode select input; active HIGH on/off track detector input DRAM read cycle divide-by-2 input; active HIGH shock detected output; active HIGH when shock is detected DESCRIPTION correction flag input from CD decoder
SAA7346
rotational shock busy output; active HIGH when rotational shock is detected synthetic new subcode frame output reset enable input; active LOW microcontroller interface input/output data line microcontroller interface clock input microcontroller interface read/write input FIFO write enable output; active HIGH open drain output; active LOW; when in by-pass mode KILLOUT equals KILL I2S data output I2S bit clock output I2S word clock output supply voltage 1 supply ground 1 DRAM address bus output 4 DRAM address bus output 3 DRAM address bus output 5 DRAM address bus output 2 DRAM address bus output 6 DRAM address bus output 1 DRAM address bus output 7 DRAM address bus output 0 DRAM address bus output 8 DRAM address bus output 9 DRAM enable output; active LOW DRAM row address strobe output; active LOW DRAM column address strobe output; active LOW DRAM write enable output; active LOW
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Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
SYMBOL D3 to D0 VSS2 VDD2
PIN 39 to 42 43 44 DRAM data bus inputs/outputs supply ground 2 supply voltage 2
DESCRIPTION
44 V DD2
VSS2
37 CAS
38 WE
40 D2
39 D3
D0
41 D1
OE 35
43
42
36
CFLG KILL SCLI WCI SDI CONFIG CLKIN TMS OTD
1 2 3 4 5 6 7 8 9
34
A9
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RAS
33 32
A8 A0
31 A7 30 29 A1 A6 A2 A5 A3 A4 VSS1 VDD1
SAA7346
28 27 26 25 24 23
RCD2 10 SSD 11
SDO 20
SCLO 21
S_NSF 13
RESET 14
KILLOUT 19
WCO 22
RSB 12
SIDA 15
SICL 16
SILD 17
FILL 18
MGB430
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION I2S input/output interfaces The SAA7346 contains an asynchronous serial input and a serial output interface. The serial operation of the interfaces is under hardware control of the external circuitry and uses the I2S protocol. The output presents a continuous clock signal SCLO (typically 2.8224 MHz) which is divided from the system clock, and a word select signal WCO, typically 44.1 kHz (fs), which is used to distinguish between right and left channels. When in by-pass mode WCO and SCLO are the same as the input interface signals WCI and SCLI, enabling data to pass through the SAA7346. Since the serial input port is asynchronous the device is independent of the CD July 1994 5
decoder clock speed and enables the word clock to vary from 1.1 x fs to 4 x fs (typically 2 x fs). This is a requirement of any electronic shock absorbing system since the disc must be rotating faster than usual to assure the FIFO is full to absorb a shock. The falling edge of WCO indicates the start of a new transfer. Data is exchanged over the SDI and SDO pins. The SAA7346 is compatible with a variety of DAC ICs. New subcode frame regeneration The SAA7346 has a digital phase-locked loop (PLL) system which decodes the F1 and F6 flags, from the first 1-bit signal generated by the CD decoder correction flag output shown in Fig.3. The F1 flag is the absolute time sync signal of the New Subcode Frame (NSF). It relates
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
the position of the subcode-sync to the audio data. This signal determines the accuracy with which the SAA7346 sews audio data together after a shock. When the CD decoder preforms a jump the NSF will be missed. The PLL system will insert the missing pulse. The resulting signal is the S_NSF which can be used as a time out for reading the
SAA7346
subcode from the decoder shown in Fig.4. The S_NSF is available externally and the NSF flag can be read via the serial microcontroller interface. The F6 flag indicates at least one hold has occurred in the decoder's error corrector and interpolator. The shock processor uses this signal to evaluate whether a shock has occurred.
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11.3 s CFLG F1 F2 F3 F4 F5 F6 F7
45.4 s F1
MGA370
Fig.3 CFLG input timing diagram.
0.37 ms
handbook, full pagewidth
6.6 ms
S_NSF
NSF
MGB431
Variable NSF is set until read by the microcontroller
Fig.4 S_NSF output timing diagram; n = 2.
Shock processor The shock processor determines whether a shock has occurred by processing all the shock detectors. The SAA7346 will enter shock mode and set SSD when the: * Csd flag is set by the microcontroller in the command register * OTD input is active while the jmp_bz flag is not set * RSB output is set while the e_rot_sd flag is set * NSF pulse is lost and the full flag is not read by the microcontroller from the status register. When the target position has been found the microcontroller should set the PFB flag in the command register. The SAA7346 will respond by clearing the SSD flag and start refilling. If CFLG still indicates a hold, the
decoder is rolling out of its FIFO. RSB will be set which sets SSD again thus the FIFO will not start refilling. The microcontroller should jump one track back and look for the correct target position again. When the motor speed is stable and the decoder does not roll out of its FIFO, the audio data will be glued together. SSD will be reset whenever the microcontroller sets PFB or the flush flags in the command register, or when the FIFO empties while the echo flag is LOW. Note if the microcontroller wants SSD to be clear for a while the shock detectors should be inhibited. FIFO controller and monitor The SAA7346 uses a state machine to control and monitor the conditions of the FIFO shown in Fig.5.
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Preliminary specification
Shock absorbing RAM addresser
SAA7346
handbook, full pagewidth
flush + reset + (empty and echo)
RESET 0
flush + reset
flush + reset HOLD 6 SSD and (NSF + S_NSF) SSD PFB PFB first nibble FILL 1
reset and sow full FILL 2
SSD SHOCK 7 SSD
SSD NSF + S_NSF
HOLD 5
HOLD 4
first nibble
FILL 3
MGB432
Fig.5 State machine flow diagram.
During normal operation the FIFO will fill up because writing is carried out twice as fast as reading; this is the fill mode. If the FIFO is full the monitor will detect and set the full flag. At the same time the fill flag will be reset thus preventing audio data from being written in to the FIFO. When the microcontroller reads the full flag from the status register, the servo control should jump back one track. The microcontroller enters a wait loop until the same absolute time subcode frame turns by again; this is the hold mode. When the spot is found again the microcontroller should set the PFB flag in the command register and the SAA7346 will resume writing to the DRAM. While in fill mode the write pointer address is saved at the end of each subcode frame. When the player exists hold mode it restores the saved address and continues writing after the last sample. Table 1 SAA7346 microcontroller interface registers. BIT 7 flush Lm BIT 6 bypass Lm1 BIT 5 echo FRM_ER
When a shock is detected the SAA7346 will enter shock mode. The shock mode will last until the PFB is set by the microcontroller or the FIFO is flushed, reset or runs empty. Microcontroller interface The SAA7346 has a 3-line microcontroller interface which is compatible with TDA1301, TDA1303 and SAA7345. WRITING DATA TO THE SAA7346 The SAA7346 command register is shown in Table 1. This can be written to via the microcontroller interface as shown in Fig.6. The command register flags functions are shown in Table 2.
REGISTER Command Status
BIT 4 jmp_bz NSF
BIT 3 otd_p full
BIT 2 e_rot_sd empty
BIT 1 Csd SSD fill
BIT 0 PFB
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Preliminary specification
Shock absorbing RAM addresser
Table 2 Command register flag functions. DESCRIPTION
SAA7346
COMMAND Flush Bypass
Flush, when set, will empty the FIFO, reset the read and write pointer addresses. Then writing will resume to the FIFO. Flag reset automatically. Bypass, when set, will power down the SAA7346. The I2S interface passes input to output directly. The parallel interface port controls RAS, CAS, WE and OE which are pulled HIGH. KILL passes directly to KILLOUT. When exiting by-pass mode the FIFO is automatically flushed. Echo, when set, will cause the FIFO contents to be continuously played until the correct position is found again. Jump busy, when set, indicates a jump is being preformed. The OTD shock detector input will be disabled. After the jump has finished the flag should be reset by a write. OTD polarity enable. Enables the polarity of the OTD input to be switched from active HIGH set, active LOW not set. Enable rotational shock detection, when set, will detect shocks whenever the decoder rolls out of its internal FIFO. Microcontroller shock detected is set when the microcontroller has detected a shock. Position Found Back, when set, indicates that the microcontroller has found the absolute time frame after a shock or hold cycle. The audio data will sew together and the flag reset automatically.
Echo jmp_bz otd_p e_rot_sd Csd PFB
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SICL SILD SIDA B7 B6 B5 B4 B3 B2 B1 B0
MGB433
Fig.6 Microcontroller WRITE timing.
Writing operation sequence: * SILD is held HIGH by the microcontroller. * Microcontroller data is clocked into the internal command register on the LOW-to-HIGH clock transition of SICL. * SILD is pulled LOW by the microcontroller to latch-in data to the command register. * SICL and SILD are pulled HIGH by the microcontroller to indicate that communications have finished.
READING STATUS OF SAA7346 The SAA7346 has a status register shown in Table 1. This can be read via the microcontroller interface shown in Fig.7. The internal status signals are made available on the SIDA pin and are shown in Table 3.
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Preliminary specification
Shock absorbing RAM addresser
Table 3 Internal status signals. DESCRIPTION
SAA7346
STATUS Lm and Lm1 FRM_ER
The two Most Significant Bits (MSB) of the FIFO. These can be used to display the FIFO length or correct the subcode time information. The FIFO length is shown in Table 4. Framing error flag is set when: 1. The microcontroller did not accept the previous subcode flag on time. When this occurs the NSF flag will be set together with FRM_ER. 2. The S_NSF generated signal does not coincide with the NSF signal generated by the decoder. When this occurs there has been a FIFO overflow in the decoder or a jump. Framing error flag is reset when status register is read.
NSF
New subcode frame is set when an absolute sync is recovered from the CFLG input. Reset when status register is read. If the NSF is still set at the next occurrence of a subcode frame, FRM_ER will be set indicating that the microcontroller has lost a frame. Full is set when the FIFO is full. When the flag is set the microcontroller must jump back to the previous track. Reset when status register is read. Empty is set when the FIFO is emptied during hold or shock modes. DRAM writing should resume immediately unless echo is set in the command register. If set, writing can only resume when PFB or flush are set in the command register. The latter will cause a discontinuity in music. Note when set there is a complete word left in the FIFO giving the SAA7346 controller time to switch to fill mode. Set shock detect is set when SAA7346 detects a shock. Fill is set when writing data to the DRAM or by setting the command register flags PFB or flush. Reset internally when full or SSD are set. FIFO length as a function of CONFIG, Lm and Lm1. CONFIG 0 0 0 0 1 1 1 1 Lm 0 0 1 1 0 0 1 1 Lm1 0 1 0 1 0 1 0 1 0.00 to 0.19 0.19 to 0.39 0.39 to 0.58 0.58 to 0.78 0.00 to 0.75 0.75 to 1.50 1.50 to 2.25 2.25 to 2.97 FIFO LENGTH (s)
Full Empty
SSD Fill
Table 4
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SICL SILD SIDA B7 B6 B5 B4 B3 B2 B1 B0
MGB434
Fig.7 Microcontroller READ timing.
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Preliminary specification
Shock absorbing RAM addresser
Read operation sequence: * SILD is held LOW by the microcontroller. * Status information is clocked from the internal status register on the LOW-to-HIGH clock transition of SICL. * SICL and SILD are pulled HIGH by the microcontroller to indicate that communications have finished. DRAM interface The SAA7346 may be connected to all standard 80 ns, 1M x 4 bit or 256K x 4 bit fast page mode DRAMs. The best performance can be expected with the 4 Mbit DRAM. The CONFIG input selects the DRAM configuration either HIGH 4 Mbit or LOW 1 Mbit format. The SAA7346 converts audio data from serial to parallel and stores it as 4 bits. The addresses for read or write actions are calculated by separate read and write pointers which are multiplexed onto a 4 bits address bus. The control signal outputs associated with the parallel inputs/outputs are shown in Table 5. Table 5 Command register flag functions. DESCRIPTION indicates write enable action row address strobe column address strobe output buffer enable for external memory during cycle. System clock
SAA7346
The system clock input, CLKIN, recommended input signal is 16.9344 MHz. The accuracy of this clock influences the accuracy of the I2S output, therefore the performance of the DAC and hence audio quality. The system clock is divided by 384 to derive the I2S output word clock, WCO divided by 8 to derive the I2S output bit clock, SCLO. Therefore whatever clock jitter the user introduces on the CLKIN signal will be reflected in the WCO and SCLO outputs. Reset Reset should be applied for four system clock cycles. Reset will: * Clear SSD * Clear the command register but leave the bypass flag set. After a reset has been applied the SAA7346 will start-up in bypass mode. Kill interface The kill interface can be used to deactivate the DAC. The kill input is passed directly to the KILLOUT output when the bypass flag in the command register is set. When the flag is not set KILLOUT is generated by the SAA7346. It is LOW after leaving bypass mode, a reset or a FIFO flush. It will be LOW until the first error free word is read from the FIFO. The kill input has no effect or function when the bypass flag is not set. Read cycle divide (RCD2) The RCD2 input enables the modes of operation shown in Table 6. When RCD2 is HIGH the DRAM-read requests are halved allowing I2S output speeds to vary. The factor n is called the over-speed factor.
COMMAND WE RAS CAS OE
When the SAA7346 leaves bypass mode where all parallel Port control lines are pulled HIGH, the device initiates a DRAM power-up routine in accordance with the JEDEC standard.
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Preliminary specification
Shock absorbing RAM addresser
Table 6 SAA7346 I2S output speeds. I2S INPUT SPEED CAV(1) n=1 n=2 n=4 n=2 n=4 I2S OUTPUT SPEED n=1 n=1 n=1 n=1 n = 12 n=
1 2
SAA7346
RCD2 LOW LOW(2) LOW LOW HIGH HIGH Notes
APPLICATION CAV CDROM player with standard audio speed delay line feature shock proof CD player high data rate CDROM/CDI player with standard audio speed musicians feature musicians feature
1. CAV with n = 4 speed at outer edge of disc; n = 1.5 at inner edge of disc. 2. To build-up a delay, RCD2 should be made HIGH temporarily for twice the delay time. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Pmax Tstg Tamb supply voltage maximum power dissipation storage temperature operating ambient temperature PARAMETER 0 - -55 -40 MIN. MAX. 6.5 500 +125 +85 V mW C C UNIT
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 80 UNIT K/W
CHARACTERISTICS VDD = 3.3 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supply VDD IDD IDDb IDDq supply voltage supply current bypass supply current quiescent supply current VDD = 5.0 V VDD = 5.0 V; bypass mode 3.3 - - - 5.0 12 4 - 5.5 - - 100 V mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital inputs INPUTS: WCI, SDI, CLKIN, OTD AND RCD2; NORMAL CMOS VIL VIH ILI CI July 1994 LOW level input voltage HIGH level input voltage input leakage current input capacitance 11 VI = 0 V to VDD -0.3 0.7VDD -10 - - - - - 0.3VDD +10 10 V A pF VDD + 0.3 V
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
SYMBOL INPUT CLKIN fclk tH tr tf VIL VIH RPU CI VIL VIH RPD CI Vthr Vthf Vhys CI tRW
PARAMETER
CONDITIONS - 35 0.8 V to (VDD - 0.8 V) (VDD - 0.8 V) to 0.8 V - -
MIN.
TYP. 16.9344 - - - - - - 50 - - - 50 - - - - -
MAX.
UNIT
system clock frequency system clock HIGH time system clock rise time system clock fall time
MHz ns ns ns
65 20 20
INPUTS: CFLG, KILL, CONFIG AND SILD; WITH PULL-UP LOW level input voltage HIGH level input voltage input pull-up resistance input capacitance VI = 0 V -0.3 0.7VDD - - -0.3 0.7VDD VI = VDD - - - 0.2VDD - - 236 0.3VDD - 10 V k pF VDD + 0.3 V
INPUT TMS; WITH PULL-DOWN LOW level input voltage HIGH level input voltage input pull-down resistance input capacitance 0.3VDD - 10 V k pF VDD + 0.3 V
INPUTS: RESET, SCLI AND SICL; SCHMITT-TRIGGER switching threshold voltage rising switching threshold voltage falling hysteresis voltage input capacitance 0.8VDD - 10 - V V V pF
0.33VDD -
INPUT RESET RESET pulse width; active LOW ns
Digital outputs OUTPUTS: FILL, S_NSF, RSB AND SSD; PUSH-PULL VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time IOL = 4 mA IOL = -4 mA 0 VDD - 0.4 - 0.8 V to (VDD - 0.8 V); - CL = 50 pF (VDD - 0.8 V) to 0.8 V; - CL = 50 pF IOL = 4 mA IOL = -4 mA 0 VDD - 0.4 - 0.8 V to (VDD - 0.8 V); - CL = 50 pF (VDD - 0.8 V) to 0.8 V; - CL = 50 pF - - - - - 0.4 VDD 50 15 15 V V pF ns ns
OUTPUTS: SDO, SCLO, WCO, WE, OE, RAS, CAS, A0 TO A9; SLEW RATE PUSH-PULL VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time - - - - - 0.4 VDD 50 20 20 V V pF ns ns
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Preliminary specification
Shock absorbing RAM addresser
SAA7346
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - -
TYP.
MAX.
UNIT
OUTPUT KILLOUT; OPEN DRAIN VOL IO CL tf LOW level output voltage output current load capacitance output fall time IOL = 2 mA 0 - - (VDD - 0.8 V) to 0.8 V; - CL = 50 pF -0.3 0.7VDD VI = 0 V to VDD IOL = 4 mA IOL = -4 mA -10 - 0 VDD - 0.4 - 0.8 V to (VDD - 0.8 V); - CL = 50 pF (VDD - 0.8 V) to 0.8 V; - CL = 50 pF -0.3 0.7VDD VI = 0 V to VDD IOL = 4 mA IOL = -4 mA -10 - 0 VDD - 0.4 - 0.8 V to (VDD - 0.8 V); - CL = 50 pF (VDD - 0.8 V) to 0.8 V; - CL = 50 pF 0.4 2 50 30 V mA pF ns
INPUTS/OUTPUTS: D0 TO D3; NORMAL CMOS WITH SLEW RATE CONTROLLED PUSH-PULL VIL VIH ILI CI VOL VOH CL tr tf LOW level input voltage HIGH level input voltage input leakage current input capacitance LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time - - - - - - - - - 0.3VDD +10 10 0.4 VDD 50 20 20 V A pF V V pF ns ns VDD + 0.3 V
INPUT/OUTPUT SIDA; NORMAL CMOS WITH PUSH-PULL VIL VIH ILI CI VOL VOH CL tr tf I2S timing RECEIVER (SEE FIG.9) LOW level input voltage HIGH level input voltage input leakage current input capacitance LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time - - - - - - - - - 0.3VDD +10 10 0.4 VDD 50 15 15 V A pF V V pF ns ns VDD + 0.3 V
Clock input SCLI
Tcy tH tL tsu th clock cycle time clock HIGH time clock LOW time 118.1(1) 41.3(1) 41.3(1) 236.2(2) - - - - 472.4(3) - - - - ns ns ns
Inputs: SDI and WCI
set-up time hold time 23.6 10 ns ns
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Preliminary specification
Shock absorbing RAM addresser
SAA7346
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TRANSMITTER (SEE FIG.8)
Clock output SCLO
Tcy tH tL td th clock cycle time clock HIGH time clock LOW time - 165.3 165.3 - 40 472.4(3) - - - - 944.8(4) - - 377 - ns ns ns
Outputs: SDO and WCO
delay time hold time ns ns
Microcontroller interface timing (see Figs 12 and 13) INPUTS: SICL AND SILD tH tL tr tf td tpd tsu1 th tsu2 input HIGH time input LOW time rise time fall time 0.8 V to (VDD - 0.8 V) (VDD - 0.8 V) to 0.8 V 180 180 - - 120 - 40 - 180 - - - - - - - - - - - 240 240 - 110 - 180 - ns ns ns ns
Read mode (see Fig.12)
delay time SILD to SIDA valid propagation delay time SICL to SIDA ns ns
Write mode (see Fig.13)
set-up time SIDA to SICL hold time SICL to SIDA set-up time SICL to SILD ns ns ns
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Preliminary specification
Shock absorbing RAM addresser
SAA7346
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TYP. -
MAX.
UNIT
DRAM interface timing (see Figs 14 and 15) Tcy tCAC tOAC th3 tRH tRL th1 th2 tCL th4 tCRd tRCd tRd tsu1 tRAh tsu2 tCAh tRh tl tRCh tRRh tWsu tWh1 tWL tWh2 tWCl tWRl tDsu tDh tDRh Notes 1. n = 4. 2. n = 2. 3. n = 1. 4. n = 12. read or write cycle time access time from CAS access time from OE OE to data input hold time RAS HIGH time RAS LOW time RAS hold time RAS hold time to OE LOW CAS LOW time CAS hold time delay time from CAS HIGH to RAS delay time from RAS to CAS RAS to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from RAS LOW column address to RAS lead time read command hold time read command hold time to RAS write command set-up time write command hold time write command LOW time write command hold time from RAS write command to CAS lead time write command to RAS lead time data output set-up time data output hold time data output hold time from RAS 160 - - 0 70 80 20 20 20 80 10 25 20 0 15 0 20 60 40 0 12 0 15 15 60 20 20 0 15 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 - - 10000 - - 10000 - - - - - - - - - - - - - - - - - - - - -
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Preliminary specification
Shock absorbing RAM addresser
SAA7346
handbook, full pagewidth
Tcy tL tH V DD - 0.8 V SCLI 0.8 V t su SDI WCI th V DD - 0.8 V 0.8 V
MGB436
Fig.8 I2S input timing.
handbook, full pagewidth
Tcy tL tH V DD - 0.8 V SCLO 0.8 V th td SDO WCO V DD - 0.8 V 0.8 V
MGB435
Fig.9 I2S output timing.
handbook, full pagewidth
SCLI
4.2336 MHz
WCI
LEFT CHANNEL 5.67 s
RIGHT CHANNEL
88.2 kHz
SDI
MGB437
MSB
LSB
MSB
LSB
Fig.10 Typical I2S data input waveform; f = 4.2 MHz; n = 2.
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Preliminary specification
Shock absorbing RAM addresser
SAA7346
handbook, full pagewidth
SCLO
2.1168 MHz
WCO
LEFT CHANNEL 11.34 s
RIGHT CHANNEL
44.1 kHz
SDO
MGB438
MSB
LSB
MSB
LSB
Fig.11 Typical I2S data output waveform; f = 2.1 MHz; n = 1.
tf
handbook, full pagewidth
tr V DD - 0.8 V
SILD 0.8 V td tr tf tH V SICL 0.8 V tL t pd V DD - 0.8 V SIDA 0.8 V
MGB439
DD
- 0.8 V
Fig.12 Microcontroller timing; READ mode.
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Preliminary specification
Shock absorbing RAM addresser
SAA7346
tf
handbook, full pagewidth
tL
tr V DD - 0.8 V
SILD 0.8 V tf tH tr t su2 V DD - 0.8 V SICL 0.8 V tL t su1 th
V DD - 0.8 V SIDA 0.8 V
MGB440
Fig.13 Microcontroller timing; WRITE mode.
July 1994
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t RL t Rh RAS 0.8 V t CRd t h4 t RCd t h1 t CL t CRd VDD - 0.8V 0.8 V t Rd t su1 A0 to A9 t RAh t su2 VDD - 0.8V ROW COLUMN 0.8 V t RCh t RRh VDD - 0.8V WE 0.8 V t h2 t OAC t CAh tl CAS
Philips Semiconductors
Shock absorbing RAM addresser
Tcy t RH VDD - 0.8V
D0 to D3
handbook, full pagewidth
19
OE t CAC
t h3
Preliminary specification
VDD - 0.8V INPUT 0.8 V
SAA7346
MGB441
Fig.14 READ cycle timing.
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SAA7346
handbook, full pagewidth
Tcy t RL t Rh t RH V - 0.8V DD 0.8 V
RAS
t CRd
t h4 t RCd t h1 t CL t CRd VDD - 0.8V 0.8 V t Rd t Rl t CAh t su2 VDD - 0.8V ROW COLUMN 0.8 V t Wsu t Wh1 t WL V DD - 0.8V t RAh
CAS
t su1 A0 to A9
WE 0.8 V t Wh2 t RWI t WCI VDD - 0.8V OE
t DRh t Dh t Dsu VDD - 0.8V D0 to D3 OUTPUT 0.8 V
MGB442
Fig.15 WRITE cycle timing.
July 1994
20
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
APPLICATION INFORMATION
SAA7346
handbook, full pagewidth
VDD 100 nF
1 M x 4 bit DRAM D3 to D0 WE CAS RAS OE 39 to 42 A9 to A0
44 43 CFLG KILL I 2S bus from CD decoder 5V 16.9 MHz CLKIN OTD RCD2 SSD 1 2 3 4 5 6 7 8 9 10 11
38 37
36 35
25 to 34
SAA7346
24 23 100 nF VDD
12 13 14 15 16 17 18 19 20 21 22
microcontroller interface S_NSF
5V 10 k
I 2S bus to DAC
MGB443
RSB
RESET
KILLOUT
Fig.16 SAA7346 application diagram.
July 1994
21
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
PACKAGE OUTLINE
SAA7346
handbook, full pagewidth
seating plane
0.1 S
S
12.9 12.3 44 1 34 33 1.2 (4x) 0.8 B
pin 1 index 0.8
11 12 0.40 0.20 10.1 9.9 22
23
0.40 0.20
0.15 M A
1.2 (4x) 0.8
0.15 M B
10.1 9.9
12.9 12.3
X
0.8
A
0.85 0.75 1.85 1.65 0.25 0.05 0.25 0.14 2.10 1.70
MBB944 - 2
detail X
0.95 0.55
0 to 10 o
Dimensions in mm.
Fig.17 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm; (SOT307-2; QFP44).
July 1994
22
Philips Semiconductors
Preliminary specification
Shock absorbing RAM addresser
SOLDERING Plastic quad flat-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be
SAA7346
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
July 1994
23
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2327, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H., P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., Components Div., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Components Dept, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS COMPONENTS S.r.l., Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.3302, Fax. (02)6752 3300. Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., Components Division, 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD31 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp24 Document order number: Date of release: July 1994 9397 736 30011
Philips Semiconductors

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